Integrated circuit field effect transistors are widely used in integrated circuits including but not limited to logic devices and memory devices. As the integration density of integrated circuits continues to increase, line widths of 0.2 .mu.m or less may be used in the integrated circuits.
Due to the decreasing line width, it may become increasingly difficult to detect defects in the integrated circuits. A particular problem in manufacturing integrated circuit field effect transistors is the detection of undesired conductive material on gate sidewalls and on inactive regions of the integrated circuit substrates. The formation of integrated circuit field effect transistors, including undesired conductive material on the gate sidewalls and on the inactive regions, will now be described with references to FIGS. 1-5.
FIGS. 1-5 illustrate the formation of N-channel field effect transistors. However, similar processes may be used to form P-channel field effect transistors and integrated circuits including both N-channel and P-channel field effect transistors, also referred to as CMOS integrated circuits.
Referring now to FIG. 1, isolation regions such as field oxide regions 28 are formed in an integrated circuit substrate, such as a silicon semiconductor substrate 10. The field oxide regions 28 form inactive regions of the integrated circuit substrate, and the regions therebetween define active regions of the integrated circuit substrate.
Continuing with the description of the FIG. 1, a field effect transistors is formed in the active region by forming a P-well 12 in the active region, for example using boron or other trivalent dopants. A gate oxide layer 16 and a conductive gate electrode 18 comprising for example doped polysilicon, is formed within the active region. Spaced apart source and drain regions 14 are then formed by forming two N-wells using for example pentavalent dopings. It will be understood that the source and drain regions 14 may be formed by implanting N-type dopants into the substrate using the gate electrode 18 as a mask. Alternatively, the source and drain regions 14 may be formed prior to forming the gate oxide 16 and/or gate electrode 18.
Referring now to FIG. 2, a silicon nitride film 20 is then formed on the integrated circuit substrate 10. As shown in FIG. 3, the silicon nitride film 20 is patterned to form a sidewall spacer 22 on the sidewall of the gate electrode 18. Then, as shown in FIG. 4, a conductive material such as titanium 24 is formed on the field effect transistor, including on the spaced apart source and drain regions 14, on the gate 18 and on the sidewall spacer 22.
Then, referring to FIG. 5, the titanium 24 is heated to react the titanium 24 with the silicon in the spaced apart source and drain regions to form titanium silicide source and drain contacts 26a and a titanium silicide gate contact 26b.
Still referring to FIG. 5, the remaining titanium 24 is then removed from the field oxide 28 and from the gate sidewall spacer 22 by etching, for example using sulfuric acid. The sulfuric acid reacts with the titanium to etch the titanium but does not readily react with titanium silicide, so that titanium silicide source and drain contacts 26a and gate contact 26b remain.
Unfortunately, as illustrated in FIG. 5, undesired titanium 24a may remain on the field oxide regions 28 and undesired titanium 24b may remain on the sidewall spacer, due to incomplete removal by the sulfuric acid etch. The undesired titanium 24b on the sidewall spacer 22 may cause short circuits in the integrated circuit, which can reduce the yields and/or reliability of the integrated circuit devices. Moreover, the undesired titanium 24a on the field oxide regions 28 can increase the leakage current of the field effect transistors, which can degrade the performance thereof.
Detection of undesired titanium 24a and 24b may become increasingly difficult as the size of the field effect transistors continues to shrink and the number of field effect transistors that are formed in an integrated circuit continues to increase.